1. Field of the Invention
The present invention generally relates to a solid state image sensor and more particularly is directed to a solid state image sensor in which even when a PN junction type sensor is employed as a light receiving section thereof, an afterimage or residual image can be reduced as much as possible.
2. Description of the Prior Art
It is known in the art that when a solid state image sensor employs a PN junction sensor having good sensitivity for short wavelength as its light receiving section, an afterimage or residual image is generated therein and hence the characteristics as the solid state image sensor is deteriorated. In order to prevent the residual image from being generated in the solid state image sensor employing the PN junction sensor, such a method is known that the sensor region is completely depleted and then a read out is performed. However, depleting the nearby surface of the sensor region causes a dark current to be increased due to Si-SiO.sub.2 interface level and this nearby surface to be easily affected by a floating charge in and above the oxide film, thereby giving rise to poor reliability. Moreover, in order to suppress the influence of the floating charge, it has been proposed to fulfil the shallow surface area of the sensor region with holes (in the case of N channel) to thereby stabilize the solid state image sensor. In this case, a serious consideration must be made on the fact that the sensitivity for the short wavelength is lowered.
In the previously proposed solid state image sensor, one of the reasons why the residual image is generated when the PN junction type sensor is used as its light receiving section may be considered by a so-called short channel modulation when the channel length of a read-out gate section is short (less than 2 to 3.mu.m). The mechanism under which the residual image is caused when the channel length of the read-out gate section is short will hereinafter be described. First, the outline of the previously proposed solid state image sensor will be described with reference to the drawings.
As shown in FIG. 1, the solid state image sensor consists of a photosensitive region 3 which includes a group of plural vertical shift registers 1 formed of a charge transfer device, for example, CCD (charge coupled device) and photoelectric converting sections, which are located between the adjacent vertical shift registers 1 and capable of accumulating charges, namely, light receiving sections 2, each being corresponding to each picture element, a storage section 5 having a group of vertical shift registers 4 similarly formed of a CCD, each of which is electrically connected to one end of each vertical shift register 1 in the photosensitive region 3, and a horizontal shift register 6 formed similarly of a CCD and which is connected to the storage section 5. In the photosensitive region 3, a read-out gate section 7 is formed on one side of each light receiving section 2, namely, the side of the corresponding vertical shift register 1 to transfer a signal charge from the light receiving section 2 to the vertical shift register 1, while an overflow drain region 9 is formed on the other side of each light receiving section 2 through an overflow control gate section 8. A channel stop region 10 is formed so as to separate each vertical line and each light receiving section 2. Other portions than the light receiving section 2 are all shielded or masked from a light.
FIG. 2A (corresponding to a cross-sectional diagram taken along a line A--A in FIG. 1) shows an example of a practical structure of the portion through which the signal charge of the light receiving section 2 is transferred to the vertical shift register 1. In this embodiment, an N.sup.+ type region 12 is formed on the major surface of a, for example, P type semiconductor substrate 11 to form the light receiving section 2 of a PN junction type. An N type region 13 is formed on the substrate 11 adjacent to the light receiving section 2 to thereby provide the vertical shift register 1 of a so-called buried channel type. Onto the vertical shift register 1 is deposited a transfer electrode 15 of, for example, two-phase drive type through an insulated layer 14 formed on the substrate 11. The transfer electrode 15 is extended over the read-out gate section 7 between the light receiving section 2 and the vertical shift register 1. The overflow control gate section 8 adjacent to the other side of the light receiving section 2 is constructed such that a control gate electrode 16 is deposited through the insulated film 14 onto the substrate 11. The overflow drain region 9 formed of an N.sup.+ type region 17 is formed to adjoin the overflow control gate section 8. The channel stop region 10 is formed of P.sup.+ type region.
In such solid state image sensor, a signal charge accumulated in the light receiving section 2 during the light receiving period is transferred to the vertical shift register 1 from the light receiving section 2 during the vertical blanking period, and then transferred therefrom to the storage section 5 at higher speed and then stored therein temporarily. Thereafter, the signal charge of one horizontal line each is transferred from the storage section 5 to the horizontal shift register 6 at each horizontal scanning period and then the signal charge is read out sequentially from the output terminal by one picture element amount each. According to this solid state image sensor, the signal charge produced in the light receiving section 2 is transferred to the light-shielded vertical shift register 1, the signal charge is then transferred from the vertical shift register 1 to the storage section 5 at high speed and the signal charge stored temporarily in the storage section 5 is outputted through the horizontal shift register 6 at each horizontal line amount. Thus, such an advantage is effected that a picture quality can be prevented from being deteriorated by a so-called smear. A conventional drive method of such solid state image sensor is as follows. As shown in a timing chart of FIG. 3, after the light having been received, the vertical shift register 1 is driven by transfer clock signals .phi..sub.A1 and .phi..sub.B1 during the first period of the corresponding vertical blanking period T.sub.0 in the odd or even field to be read out to thereby perform a so-called discharge-transfer of undesired charge in the vertical shift register 1. Then, a read pulse P.sub.1 is applied to one of the transfer electrodes for the vertical shift register 1 to open the read-out gate section 7 to thereby transfer the signal charge from the light receiving section 2 to the vertical shift register 1. Subsequently, transfer clock signals .phi..sub.A2 and .phi..sub.B2 are applied to the vertical shift register 1 to transfer the signal charge from the vertical shift register 1 to the storage section 5, and then the solid state image sensor enters into the light receiving period.
The mechanism of how the residual image is produced in such solid state image sensor will be described below. When the light receiving section 2 is formed of PN junction type, as shown in FIG. 2B, as the reference potential of the light receiving section 2, the surface potential .phi..sub.S of the read-out gate section 7 upon reading out the signal charge in the preceding frame becomes a reference potential when a signal charge Q.sub.sig of the next frame is accumulated, so that the reset potential of the light receiving section 2 must always be made constant. In FIG. 2B, reference numeral 21 denotes a potential when the charge is transferred from the vertical shift register 1 to the storage section 5 and reference numeral 22 denotes a potential when the charge is read out from the light receiving section 2 into the vertical shift register 1. However, as shown in FIG. 2C (which diagram shows the potential when the signal charge is read out from the light receiving section 2 to the vertical shift register 1), the surface potential of the read-out gate section 7 is modulated by the potential of the vertical shift register 1 as the channel length l of the read-out gate section 7 becomes short. In other words, since the potential of the vertical shift register 1 is determined by the signal charge of the preceding frame and the surface potential of the read-out gate section 7 is modulated by the potential of the vertical shift register 1 to thereby determine the reference potential of the light receiving section 2 in the subsequent frame, the signal charge amount of the subsequent frame is affected by the preceding frame to appear as the residual image. In FIG. 2C, if, for example, a signal charge Q.sub.S (.sub.n-2) of (n-2)-th frame is equal to 0, the potential of the vertical shift register 1 thereof is taken as V.sub.D and the surface potential of the read-out gate section 7 thereof is taken as .phi..sub.S, a reference potential of the light receiving portion 2 in the subsequent (n-1)-th frame is determined by the surface potential .phi..sub.S. When the signal charge Q.sub.S (.sub.n-1)=Q.sub.S of this (n-1)-th frame is transferred to the vertical shift register 1 and its potential becomes equal to V.sub.D ', the surface potential of the read-out gate section 7 is modulated from .phi..sub.S to .phi..sub.S ' by this potential V.sub.D ', leaving a part of the charge of the (n-1)-th frame corresponding to .DELTA..phi..sub.S in the light receiving section 2. Accordingly, since the surface potential .phi..sub.S ' of the read-out gate section 7 becomes the reference potential of the light receiving section 2 in the following n-th frame, the remaining charge corresponding to the .DELTA..phi..sub.S pertains the generation of the residual image.